Aldec Boosts VHDL/Verilog Simulation Performance with the Release of Riviera 2002.02

By Optimizing Its Industry-Proven Common-Kernel Simulator, Aldec Speeds Riviera up to 4x


Henderson Nevada, February 15th, 2002 -- Aldec, Inc., a leading supplier of HDL design entry and verification tools for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), announced today the release of Riviera 2002.02 with vastly improved performance and several new productivity enhancement features. The Riviera product is based on Aldec’s VHDL and Verilog mixed-language simulation technology, used by ASIC and high-density FPGA designers for new generation system-on-chip designs.

Increased Performance
Building on the success of Riviera’s previous releases, Aldec has reached a new level of performance, making it ideal for server farms and long regression testing where performance is essential. Riviera 2002.02 supports UNIX, Linux and Windows NT/XP and the performance increases were achieved on all platforms.

“We have improved what was already a very fast mixed HDL language simulator, opening it to new markets in regression testing,” stated Eric Seabrook, Product Marketing Manager for Aldec, adding, “we are also offering design teams maximum performance with the most flexibility.”

Added Features
In addition to the VHDL and Verilog performance improvements in Riviera 2002.02, Aldec has also optimized the VHPI/PLI interfaces that are used with other leading “best-in-class” verification tools such as debuggers and testbench generators. New waveform enhancements, macro commands and support for SWIFT(tm) MemPro and Denali memory models are also included.

Availability
Riviera includes a Library Manager, HDL Editor, Waveform Viewer, and the choice of a VHDL, Verilog or mixed simulation kernel. The first year’s maintenance is included in the initial sale price. Riviera is sold directly by Aldec in the U.S. and authorized international distributors. To receive a FREE evaluation copy of Riviera, go to www.aldec.com/riviera.


About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.

Riviera is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Contact:        Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224
                erics@aldec.com